The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A first system on a chip (SOC) can communicate with a second SOC using inter-chip communication protocols. As an example, in a peripheral component interconnect express (PCIe) domain PCIe protocols can be used for communication between SOCs. The SOCs can include respective PCIe interfaces. The PCIe interfaces communicate with each other on a single channel based on the PCIe protocols and according to PCIe ordering rules. The channel is used for transmitting read and write requests between the PCIe interfaces. The PCIe interfaces share the channel, such that (i) read and write requests of the first SOC and corresponding read completion data, and (ii) read and write requests of the second SOC and corresponding read completion data, are transmitted over the same channel. Read completion data refers to data read from a first SOC (or responder) to satisfy a read request received from a second SOC (or requestor).
The read and write requests transmitted between the PCIe interfaces are implemented according to the PCIe ordering rules. The PCIe ordering rules allow the PCIe interfaces to determine the order in which to execute multiple read requests, multiple write requests and/or a combination of a read request and a write request. For example, if a PCIe interface receives a read request and a write request, the PCIe ordering rules allow the interface to determine which one of the read request and the write request to perform prior to performing the other one of the read request and the write request.
Modules, devices, buses and/or other elements within a SOC may communicate with each other using intra-chip (or on-chip) communication protocols. As an example, advanced microcontroller bus architecture (AMBA) protocols, such as advanced extensible interface (AXI) protocols can be used in an AXI domain to communicate between elements within a SOC. An SOC may have any number of elements. Communication between each pair of the elements can be performed using, for example, three channels. The first and second channels are used for sending respectively read requests and write requests between the elements. The third channel can be used for sending response signals to the read and write requests.
Although AXI protocols include AXI ordering rules, the AXI ordering rules are more relaxed than the PCIe ordering rules. The AXI ordering rules allow the elements of a SOC to determine the order in which to execute multiple read requests and multiple write requests. The AXI ordering rules do not allow a SOC to determine in which order to perform a combination of a read request and a write request. The third channel is used in the AXI domain to indicate when a previous request is satisfied. This allows an element to determine when to send the next request and prevents, for example, a read request from overtaking a write request.
For example, a first element in a SOC can issue a write request to write data to a second element in the SOC. The first element then issues a read request to read the data back from the second element. The write request and the read request can be transmitted on different channels in the AXI domain and can have associated transmission and execution delays, which can vary. Since the delays can vary and since the AXI protocols do not include ordering rules for a combination of received write and read requests, the read request may overtake the write request (referred to as a race condition). A read request overtakes a write request when the write request was issued before the read request and the read request is received and/or processed prior to receiving and/or processing the write request. If a read request overtakes a write request, previously written data can be read back instead of reading back the data being written as a result of the write request.
A race condition can occur unless precautionary tasks are performed. As an example, a first element of an SOC can wait for a write response from the second element before sending a read request to the second element. The write response indicates to the first element that the write request has been received and is being processed. This assures that the read request does not overtake the write request.